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5410a?hirel?10/04 features superscalar (3 instructions per clock peak) dual 16 kb caches selectable bus clock 32-bit compatibility po werpc implementation on-chip debug support nap, doze and sleep power saving modes device offered in cerquad, cbga 255 and ci-cga 255 features specific to cb ga 255 and ci-cga 255 7.4 specint95, 6.1 specfp95 at 300 mhz (estimated) p d typically = 3.5w (266 mhz), full operating conditions branch folding 64-bit data bus (32-bit data bus option) 4-gbytes direct addressing range pipelined single/double precision float unit ieee 754 compatible fpu ieee p 1149-1 test mode (jtag/c0p) f int max = 300 mhz f bus max = 75 mhz compatible cmos input/ttl output features specific to cerquad 5.6 specint95, 4 specfp95 and 200 mhz (estimated) p d typically = 2.5w (200 mhz), full operating conditions description the pid7t-603e implementation of the powerpc 603e (renamed after the 603r) is a low-power implementation of the reduced instruction set computer (risc) micropro- cessor powerpc family. the 603r is pin-to-pin compatible with the powerpc 603e and 603p in a cerquad package. the 603r implements 32-bit effective addresses, integer data types of 8, 16 and 32 bits, and floating-point data types of 32 and 64 bits. the 603r is a low-power 2.5/3.3v design and provides four software controllable power-saving modes. this device is a super scalar processor capable of issuing and retiring as many as three instructions per clock. instructions can be executed in any order for increased performance, but, the 603r makes completion appear sequential. it integrates five execution units and is able to execute five instructions in parallel. the 603r provides independent on-chip, 16-kbyte, four-way set-associative, physi- cally addressed caches for instructions and data, as well as on-chip instructions, and data memory management units (mmus). the mmus contain 64-entry, two-way set-associative, data and instruction translation look aside buffers that provide support for demand-paged virtual memory address translation and variable-sized block trans- lation. the 603r has a selectable 32- or 64-bit data bus and a 32-bit address bus. the inter- face protocol allows multiple masters to compete for system resources through a central external arbiter. the device s upports single-beat and burst data transfers for memory accesses, and supports memory-mapped i/os. the 603r uses an advanced, 2.5/3.3v cmos process technology and maintains full interface compatibility with ttl devices. it also integrates in- system testability and debugging features through jt ag boundary-scan capabilities. powerpc ? 603e risc microprocessor family pid7t-603e tspc603r rev. 5410a?hirel?10/04
2 tspc603r 5410a?hirel?10/04 screening/quality/ packaging this product is manufactur ed in full compliance with: ci-cga 255 and cerquad: mil-prf-38535 class q or according to atmel standards cbga 255: upscreenings based upon atmel standards full military temperature range (t c = -55c, t c = +125c) industrial temperature range (t c = -40c, t c = +110c) cerquad: commercial temperature ranges ( t c = 0 c, t c = +70 c) internal/io power supply = 2.5 5% // 3.3v 5% 255-lead cbga package and 255-lead cbga with sci (ci-cga) package block diagram figure 1. block diagram g suffix cbga 255 ceramic ball grid array gs suffix ci-cga 255 ceramic ball grid array with solder column interposer (sci) cerquad 240 a suffix cerquad 240 ceramic leaded chip carrier cavity up completion unit fetch unit dispatch unit branch unit integer unit gen reg unit gen re- name load/ store unit fp re- name fp reg file float unit d mmu 16k data cache i mmu 16k inst. cache bus interface unit system bus 32b address 64b data
3 tspc603r 5410a?hirel?10/04 overview the 603r is a low-power implementation of the powerpc microprocessor family of reduced instruction set computing (risc) microprocessors. the 603r implements the 32-bit portion of the powerpc architecture, which provides 32-bit effective addresses, integer data types of 8, 16 and 32 bits, and floating-point data types of 32 and 64 bits. for 64-bit powerpc microprocessors, the powe rpc architecture prov ides 64-bit integer data types, 64-bit addressing, and other features required to complete the 64-bit architecture. the 603r provides four software controllable power-saving modes. three of the modes (nap, doze, and sleep) are static in nature, and progressively reduce the amount of power dissipated by the processor. the fourth is a dynamic power management mode that causes the functional units in the 603r to automatically enter a low-power mode when the functional units are idle without affecting operational performance, software execution, or any external hardware. the 603r is a superscalar processor capable of issuing and retiring as many as three instructions per clock. instructions can be executed in any order for increased perfor- mance, but, the 603r makes completion appear sequential. the 603e integrates five execution units: an integer unit (iu) a floating-point unit (fpu) a branch processing unit (bpu) a load/store unit (lsu) a system register unit (sru) the ability to execute five inst ructions in parallel and the us e of simple instructions with rapid execution times yield high effici ency and throughput for 603r-based systems. most integer instructions execute in one cl ock cycle. the fpu is pipelined so a sin- gle-precision multiply-a dd instruction can be issued every clock cycle. the 603r provides independent on-chip, 16 kbyte, four-way set-associative, physically addressed caches for instructions and data, as well as on-chip instruction and data memory management units (mmus). the mmus contain 64-entry, two-way set-associa- tive, data and instruction translation lookaside buffers (dtlb and itlb) that provide support for demand-paged virtual memory addre ss translation and variable-sized block translation. the tlbs and caches use a least recently used (lru) replacement algo- rithm. the 603r also supports block address translation through the use of two independent instruction and data block address translation (ibat and dbat) arrays of four entries each. effective addresses are compared simultaneously with all four entries in the bat array during block translation. in accordance with the powerpc architecture, if an effective address hits in both the tlb and bat array, the bat translation has priority. the 603r has a selectable 32- or 64-bit data bus and a 32-bit address bus. the 603r interface protocol allows multiple masters to compete for system resources through a central external arbiter. the 603r provides a three-state coherency protocol that sup- ports the exclusive, modified, and invalid cache states. this protocol is a compatible subset of the mesi (modified/exclusive/shar ed/invalid) four-state protocol and operates coherently in systems that contain four -state caches. the 603r supports single-beat and burst data transfers for memory accesses, and supports memory-mapped i/os. the 603r uses an advanced, 0.29 m 5-metal-layer cmos process technology and maintains full inte rface compatibility with ttl devices.
4 tspc603r 5410a?hirel?10/04 signal description figure 2, tables 8 and 9 on page 19 describe the signals on the tspc603r and indi- cate signal functions. the test signals, trst , tms, tck, tdi and tdo, comply with the subset p-1149.1 of the ieee testability bus standard. the three signals lssd_mode , li_tstclk and l2_tstclk are test signals for fac- tory use only and must be pulled up to v dd for normal machine operations. figure 2. functional signal groups br bg abb ts tt[0-4] ap[0-3] ape tbst tsiz[0-2] gbl ci wt cse[0-1] tc[0-1] aack artry sysclk clk_out pll_cfg[0-3] dbg dbwo dbb dpe dp[0-7] dh[0-31], dl[0-31] a[0-31] dbdis ta dr tr y tea int, smi mcp hreset, sreset ckstp_in, ckstp_out rsrv qreq, qack tben tlbisync trst, tck, tms, tdi, td0 5 lssd_mode l1_tstclk, l2_tstclk 3 1 1 1 vdd ovdd gnd avdd address arbitration address start address bus transfer attribute address termination clocks processor status lssd test control power supply 64 8 1 1 1 1 1 2 1 2 2 1 2 1 1 20 19 40 1 1 1 1 1 1 1 32 4 1 5 3 1 1 1 2 4 1 2 1 1 603r voltdetgnd 1 power supply indicator data attribution data transfer data termination interrupts checkstops reset jtag/cop interface
5 tspc603r 5410a?hirel?10/04 detailed specifications this specification describes the specif ic requirements for the microprocessor tspc603r, in compliance with mil-std-883 class b or atmel standard screening. applicable documents 1. mil-std-883: test methods and procedures for electronics 2. mil-prf-38535: general spec ifications for microcircuits the microcircuits are in accordance with the applicable documents and as specified herein. design and construction terminal connections depending on the package, the terminal connec tions are as shown in table 5 on page 14, table 7 on page 17, ?recommended operating conditions? on page 6, figure 17 on page 47, figure 19 on page 49 and figure 2 on page 4. lead material and finish lead material and finish shall be as specified in mil-std-1835. (see ?package mechanical data? on page 46.) absolute maximum ratings absolute maximum ratings are stress ratings only and functional operation at the maxi- mum is not guaranteed. stresses beyond those listed may affect device reliability or cause permanent damage to the device. notes: 1. caution : the input voltage must not be greater than ov dd by more than 2.5v at any time, including during power-on reset. 2. caution : the ov dd voltage must not be greater than v dd /av dd by more than 1.2v at any time, including during power-on reset. 3. caution : the v dd /av dd voltage must not be greater than ov dd by more than 0.4v at any time, including during power-on reset. functional operating conditions are given in ac and dc electrical specifications. stresses beyond the absolute maximums listed may affect device reliability or cause permanent damage to the device. absolute maximum ratings for the 603r (1)(2)(3) parameter symbol min max unit core supply voltage v dd -0.3 2.75 v pll supply voltage av dd -0.3 2.75 v i/o supply voltage ov dd -0.3 3.6 v input voltage v in -0.3 5.5 v storage temperature range t stg -55 +150 c
6 tspc603r 5410a?hirel?10/04 recommended operating conditions the following are the recommended and tested operating conditions. proper device operation outside of these ranges is not guaranteed. thermal characteristics cbga 255 and ci-cga 255 packages the data found in this section concerns 603r devices packaged in the 255-lead 21 mm multi-layer ceramic (mlc) and ceramic bga package. data is included for use with a thermalloy #2328b heat sink. the internal thermal resistance for this package is negligible due to the exposed die design. a thermal interface material is recommended at the package lid to heat sink interface to minimize the thermal contact resistance. additionally, the cbga package offers an ex cellent thermal connection to the card and power planes. heat generated at the chip is dissipated through the package, the heat sink (when used) and the card. the parallel heat flow paths result in the lowest overall thermal resistance as well as offer significantly better power dissipation capability if a heat sink is not used. the thermal characteristics for the flip-chip cbga and ci-cga packages are as follows: thermal resistance (junction-to-case) = r jc or jc = 0.095 c/watt for the 2 packages. thermal resistance (j unction-to-ball) = r jb or jb = 3.5 c/watt for the cbga package. thermal resistance (junction-to-bottom sci) = r js or js = 3.7 c/watt for the ci-cga package. the junction temperature can be calculated from the junction to ambient thermal resis- tance, as follow: junction temperature: t j = t a + (r jc + r cs + r sa ) p where: t a is the ambient temperature in the vicinity of the device r jc is the die junction to case thermal resistance of the device r cs is the case to heat sink thermal resistance of the interface material r sa is the heat sink to ambient thermal resistance p is the power dissipated by the device during operation, the die-junction temperatures (t j ) should be maintained at a lower value than the value specified in ?recommended operating conditions? on page 6. recommended operating conditions parameter symbol min max unit core supply voltage v dd 2.375 2.625 v pll supply voltage av dd 2.375 2.625 v i/o supply voltage ov dd 3.135 3.465 v input voltage v in gnd 5.5 v operating temperature t c -55 +125 c junction operating temperat ure specific to cerquad t j ?+135 c
7 tspc603r 5410a?hirel?10/04 the thermal resistance of the thermal interface material (r cs ) is typically about 1 c/watt. assuming a t a of 85 c and a consumption (p) of 3.6 watts, the junction temperature of the device would be as follow: t j = 85 c + (0.095 c/watt + 1 c/watt + r sa ) 3.5 watts. for the thermalloy heat sink #2328b, the heat sink-to-ambient thermal resistance (r sa ) versus airflow velocity is shown in figure 3. figure 3. cbga thermal management example assuming an air velocity of 1 m/sec, the asso ciated overall thermal resistance and junc- tion temperature, found in table 1 will result. vendors such as aavid, thermalloy ? , and wakefield engineering can supply heat sinks with a wide range of thermal performance. cerquad 240 package this section provides thermal management data for the 603r. this information is based on a typical desktop configuration using a 240 lead, 32 mm x 32 mm, wire-bond cer- quad package with the cavity up (the silicon die is attached to the bottom of the package). this configuration enables dissipation through the pcb. the thermal characteristics for a wire-bond cerquad package are as follows: thermal resistance (junction to bottom of the case) (typical) = r jc or jc = 2.5 c/watt thermal resistance (junction to top of the case) is typically 25 c/w table 1. thermal resistance and junction temperature configuration r ja (c/w) t j (c) with 2328b heat sink 5 106 0 1 2 3 4 5 6 7 heat sink thermal resistance approach air velocity (m/sec) rsa ( c/w) 0123
8 tspc603r 5410a?hirel?10/04 thermal management example the junction temperature can be calculated from the junction to ambient thermal resis- tance, as follows: junction temperature: t j = t c + r jc p t j = t a + (r cs + r sa ) p + r jc p so t j = t a + (r jc + r cs + r sa ) p where: t a is the ambient temperature in the vicinity of the device r ja is the junction to ambient resistance r jc is the junction to case thermal resistance of the device r cs is the case to heat sink thermal resistance of the interface material r sa is the heat sink to ambient thermal resistance p is the power dissipated by the device because dissipation is made through the pcb, r cs and r sa are user values, and can vary considerably depending on the customer?s application. in a typical customer application, if r cs is 0.5 c/w, r sa is 3 c/w and ta is 110 c, t j can be estimated. t j = 110 c + (2.5 + 0.5 + 3) 2.5 = 125 c note that verification of external thermal resistance and case temperature should be performed for each application. thermal resistance depends on many factors including the amount of air turbulence and can therefore vary considerably. power consideration the powerpc 603r is a microprocessor spec ifically designed for low-power operation. like the 603e microprocessor version, the 603r provides both automatic and pro- gram-controllable power reduction modes for progressive reduction of power consumption. this section describes the hardware support provided by the 603r for power management. dynamic power management dynamic power management automatically powers up and down the individual execu- tion units of the 603r, based upon the contents of the instruction stream. for example, if no floating-point instructions are being execut ed, the floating-point unit is automatically powered down. power is not actually removed from the execution unit; instead, each execution unit has an independent clock inpu t, which is automatically controlled on a clock-by-clock basis. since cmos circuits consume negligible power when they are not switching, stopping the clock to an execution unit effectively eliminates its power con- sumption. the operation of dpm is completely transparent to software or any external hardware. dynamic power management is enabled by setting bit 11 in hid0 on power-up, following hreset .
9 tspc603r 5410a?hirel?10/04 programmable power modes the 603r provides four programmable power states ? full power, doze, nap and sleep. the software selects these modes by setting one (and only one) of the three power sav- ing mode bits. the hardware can enable a power management state through external asynchronous interrupts. the hardware interrupt causes the transfer of program flow to interrupt the handler code. the appropriate mode is then set by the software. the 603r provides a separate interrupt and interrupt vector for power management?the system management interrupt (smi). the 603r also contains a decrement timer which allows it to enter the nap or doze mode for a predetermined amount of time and then return to full power operation through the decrementer interrupt (di). note that the 603r cannot switch from power-on management mode to another without first returning to full on mode. the nap and sleep modes disable bus snooping; therefore, a hardware hand- shake is provided to ensure coherency before the 603r enters these power management modes. table 2 summarizes the four power states. note: 1. exceptions are referred to as interr upts in the architecture specification power management modes the following describes the characteristics of the 603r?s power management modes, the requirements for entering and exiting th e various modes, and the system capabilities provided by the 603r while the power management modes are active. full power mode with dpm disabled full power mode with dpm disabled; power mode is selected when the dpm enable bit (bit 11) in hid0 is cleared default state following power-up and hreset all functional units are operating at full processor speed at all times full power mode with dpm enabled full power mode with dpm enabled (hid0[11] = 1); provides on-chip power manage- ment without affecting the functionality or performance of the 603r required functional units are operating at full processor speed functional units are clocked only when needed no software or hardware intervention required after mode is set software/hardware and performance are transparent table 2. power pc 603r microprocessor programmable power modes pm mode functioning units activatio n method full-power wake-up method full power all units active ?? full power (with dpm) requested logi c by demand by instruction dispatch ? doze - bus snooping - data cache as needed - decrementer timer controlled by sw external asynchronous exceptions (1) decrementer interrupt reset nap decrementer timer controlled by hardware and software external asynchronous exceptions decrementer interrupt reset sleep none controlled by hardware and software external asynchronous exceptions reset
10 tspc603r 5410a?hirel?10/04 doze mode the doze mode disables most functional units but maintains cache coherency by enabling the bus interface unit and snooping. a snoop hit w ill cause the 603r to enable the data cache, copy the data back to the memory, disable the cache, and fully return to the doze state. in this mode: most functional units are disabled bus snooping and time base/ decrementer ar e still enabled dose mode sequence: ? set doze bit (hid0[8) = 1) ? 603r enters doze mode after several processor clocks there are several methods for returning to full-power mode ?assert int , smi , mcp or decrementer interrupts ? assert hard reset or soft reset the transition to full-power state takes no more than a few processor cycles phase locked loop (pll) running and locked to sysclk nap mode the nap mode disables the 603r but still ma intains the phase locked loop (pll) and the time base/decrementer. the time base can be used to restore the 603r to full-on state after a programmed amount of time. because bus snooping is disabled for nap and sleep modes, a hardware handshake using the quiesce request (qreq ) and quiesce acknowledge (qack ) signals is required to maintain data coherency. the 603r will assert the qreq signal to indicate that it is ready to disable bus snooping. when the system has ensured that snooping is no longer necessary, it will assert qack and the 603r will enter the sleep or nap mode. in this mode: the time base/decrementer is still enabled most functional units are disabled (including bus snooping) all non-essential input receivers are disabled nap mode sequence: ? set nap bit (hid0[9] = 1) ? 603r asserts quiesce request (qreq ) signal ? system asserts quiesce acknowledge (qack ) signal ? 603r enters sleep mode after several processor clocks there are several methods for returning to full-power mode: ?assert int , spi , mcp or decrementer interrupts ? assert hard reset or soft reset transition to full-power takes no more than a few processor cycles the pll is running and locked to sysclk
11 tspc603r 5410a?hirel?10/04 sleep mode sleep mode consumes the least amount of po wer of the four modes since all functional units are disabled. to conserve the maximum amount of power, the pll may be dis- abled and the sysclk may be re moved. due to the fully stat ic design of the 603r, the internal processor state is preserved when no internal clock is present. because the time base and decrementer are disabled while the 603r is in sleep mode, the 603r?s time base contents will have to be updated from an external time base following sleep mode if accurate time-of-day maintenance is required. before the 603r enters the sleep mode, the 603r will assert the qreq signal to indicate that it is ready to disable bus snooping. when the system has ensured that snooping is no longer necessary, it will assert qack and the 603r will enter the sleep mode. in this mode: all functional units are disabled (i ncluding bus snooping and time base) all non-essential input receivers are disabled ? internal clock regenerators are disabled ? the pll is still running (see below) sleep mode sequence ? set sleep bit (hid0[10] = 1) ? 603r asserts quiesce request (qreq ) ? system asserts quiesce acknowledge (qack ) ? 603r enters sleep mode after several processor clocks there are several methods for returning to full-power mode ?assert int , smi , or mcp interrupts ? assert hard reset or soft reset the pll may be disabled and sysclk may be removed while in sleep mode return to full-power mode after pll and sysclk disabled in sleep mode ? enable sysclk ? reconfigure pll into the desired processor clock mode ? system logic waits for pll startup and relock time (100 s) ? system logic asserts one of the sleep recovery signals (for example, int or smi) power management software considerations since the 603r is a dual issue processor with out-of-order execution capabilities, care must be taken with the way the power management mode is entered. furthermore, nap and sleep modes require all outstanding bus operations to be completed before the power management mode is entered. normally, during the system configuration time, one of the power management modes would be selected by setting the appropriate hid0 mode bit. later on, the power management mode is invoked by setting the msr[pow] bit. to provide a clean transition into and out of the power management mode, the stmsr [pow] should be preceded by a sync instruction and followed by an isync instruction.
12 tspc603r 5410a?hirel?10/04 power dissipation notes: 1. these values apply for all valid pll_cfg[0-3] settings and do not include output driver power (ov dd ) or analog supply power (av dd ). ov dd power is system dependent but is typically 10% of v dd . worst case av dd = 15 mw 2. typical power is an average value measured at v dd = av dd = 2.5v, ov dd = 3.3v, in a system execut ing typical applications and benchmark sequences 3. maximum power is measured at v dd = 2.625v using a worst-case instruction mix 4. to calculate the power consumption at low temperature (-55c), use a factor of 1.25 marking each microcircuit is legible and permanently marked with at least the following information: atmel logo manufacturer?s part number class b identification if applicable date code of inspection lot esd identifier if available country of manufacture table 3. power dissipation (1)(2)(3)(4) with v dd /a v dd = 2.5 5%v, o v dd = 3.3 5%v, gnd = 0v, 0 c t c 125 c cpu clock frequency cerquad 240 package cbga 255 and ci-cga 255 units 166 mhz 200 mhz 166 mhz 200 mhz 233 mhz 266 mhz 300 mhz full-on mode (dpm enabled) typical 2.1 2.5 2.1 2.5 3 3.5 4 w max 3.2 4 3.2 4 4.6 5.3 6 w doze mode typical 1.5 1.7 1.5 1.7 1.8 2 2.1 w nap mode typical 100 120 100 120 140 160 180 mw sleep mode typical 96 110 96 110 123 135 150 mw sleep mode-pll disabled typical 60 60 60 60 606060mw sleep mode-pll and sysclk disabled typical 25 25 25 25 252525mw maximum 60 60 60 60 60 80 100 mw
13 tspc603r 5410a?hirel?10/04 pin assignments cbga 255 and ci-cga 255 packages figure 4 (pin matrix) shows the pinout as viewed from the top of the cbga and ci-cga packages. the direction of the top surface view is shown by the side profile of the packages. figure 4. cbga 255 and ci?cga 255 top view t b c d e f g h j k l r m n p 01 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 a pin matrix top view not to scale view encapsulant substrate assembly die cbga 255 ci-cga 255
14 tspc603r 5410a?hirel?10/04 pinout listing notes: 1. ov dd inputs apply power to the i/o drivers and v dd inputs supply power to the processor core table 4. power and ground pins cbga and ci-cga pin number v dd gnd pll (av dd )a10 internal logic (1) (v dd ) f06, f08, f09, f11, g07, g10, h06, h08, h09, h11, j06, j08, j09, j11, k 07, k10, l06, l08, l09, l11 c05, c12, e03, e06, e08, e09, e11, e14, f05, f07, f10, f12, g06, g08, g09, g11, h05, h07, h10, h12, j05, j07, j10, j12, k06, k08, k09, k11, l05, l07, l10, l12, m03, m06, m08, m09, m11, m14, p05, p12 i/o drivers (1) (ov dd ) c07, e05, e07, e10, e12, g03, g05, g12, g14, k03, k05, k12, k14, m05, m 07, m10, m12, p07, p10 table 5. signal pinout listing signal name cbga and ci-cga pin number active i/o a[0-31] c16, e04, d13, f02, d14, g 01, d15, e02, d16, d04, e13, g02, e15, h01, e16, h02, f13, j01, f14, j02, f15, h 03, f16, f04, g13, k01, g15, k02, h16, m01, j15, p01 high i/o aack l02 low input abb k04 low i/o ap[0-3] c01, b04, b03, b02 high i/o ape a04 low output artry j04 low i/o bg l01 low input br b06 low output ci e01 low output ckstp_in d08 low input ckstp_out a06 low output clk_out d07 - output cse[0-1] b01, b05 high output dbb j14 low i/o dbg n01 low input dbdis h15 low input dbwo g04 low input dh[0-31] p14, t16, r15, t15, r13, r 12, p11, n11, r11, t12, t11, r10, p09, n09, t10, r09, t09, p08, n08, r08, t08, n 07, r07, t07, p06, n06, r06, t06, r05, n05, t05, t04 high i/o dl[0-31] k13, k15, k16, l16, l15, l13, l14, m16, m15, m13, n1 6, n15, n13, n14, p16, p15, r16, r14, t14, n10, p13, n1 2, t13, p03, n03, n04, r03, t01, t0 2, p04, t03, r04 high i/o dp[0-7] m02, l03, n02, l04, r0 1, p02, m04, r02 high i/o dpe a05 low output drtry g16 low input gbl f01 low i/o hreset a07 low input
15 tspc603r 5410a?hirel?10/04 notes: 1. these are test signals for factory use only and must be pulled up to ov dd for normal machine operation. 2. nc (not connected) in the 603e bga package; internally tied to gnd in the 603r bga package to indicate to the power sup- ply that a low-voltage processor is present. int b15 low input l1_tstclk (1) d11 - input l2_tstclk (1) d12 - input lssd_mode (1) b10 low input mcp c13 low input pll_cfg[0-3] a08, b09, a09, d09 high input qack d03 low input qreq j03 low output rsrv d01 low output smi a16 low input sreset b14 low input sysclk c09 - input ta h14 low input tben c02 high input tbst a14 low i/o tc[0-1] a02, a03 high output tck c11 - input tdi a11 high input tdo a12 high output tea h13 low input tlbisync c04 low input tms b11 high input trst c10 low input ts j13 low i/o tsiz[0-2] a13, d10, b12 high i/o tt[0-4] b13, a15, b1 6, c14, c15 high i/o wt d02 low output nc b07, b08, c03, c06, c08, d 05, d06, f03, h04, j16 low input voltdetgnd (2) f03 low output table 5. signal pinout listing (continued) signal name cbga and ci-cga pin number active i/o
16 tspc603r 5410a?hirel?10/04 cerquad 240 package figure 5. cerquad 240: top view completion unit fetch unit dispatch unit branch unit integer unit gen reg unit gen re- name load/ store unit fp re- name fp reg file float unit d mmu 16k data cache i mmu 16k inst. cache bus interface unit system bus 32b address 64b data
17 tspc603r 5410a?hirel?10/04 pinout listing table 6. power and ground pins cerquad pin number vcc gnd pll (av dd ) 209 internal logic 4, 14, 24, 34, 44, 59, 122, 137, 147, 157, 167, 177, 207 9, 19,29, 39, 49, 65, 116, 132, 142, 152, 162, 172, 182, 206, 239 output drivers 10, 20, 35, 45, 54, 61, 70, 79, 88, 96, 104, 112, 121, 128, 138, 148, 163, 173, 183, 194, 222, 229, 240 8, 18, 33, 43, 53, 60, 69, 77, 86, 95, 103, 111, 120, 127, 136, 146, 161, 171, 181, 193, 220, 228, 238 table 7. signal pinout listing signal name cerquad pin number a[0-31] 179, 2, 178, 3, 176, 5, 175, 6, 174, 7, 170, 11, 169, 12, 168, 13, 166, 15, 165, 16, 164, 17, 160, 21, 159, 22, 158, 23, 151, 30, 144, 37 aack 28 abb 36 ap[0-3] 231,230,227,226 ape 218 artry 32 bg 27 br 219 ci 237 ckstp_in 215 ckstp_out 216 clk_out 221 cse[0-1] 225,150 dbb 145 dbg 26 dbdis 153 dbwo 25 dh[0-31] 115, 114, 113, 110, 109, 108, 99, 98, 97, 94, 93, 92, 91, 90, 89, 87, 85 , 84, 83, 82, 81, 80, 78, 76, 75, 74, 73, 72, 71, 68, 67, 66 dl[0-31] 143, 141, 140, 139, 135, 134, 1 33, 131, 130, 129, 126, 125, 124, 123, 119, 118, 117, 107, 106, 105, 102, 101, 100, 51, 52, 55, 56, 57, 58, 62, 63, 64 dp[0-7] 38, 40, 41, 42, 46, 47, 48, 50 dpe 217 drtry 156 gbl 1 hreset 214
18 tspc603r 5410a?hirel?10/04 notes: 1. these are test signals for factory use only and must be pulled up to v dd for normal machine operation. 2. ov dd inputs supply power to the i/o drivers and v dd inputs supply power to the proces sor core. future members of the 603 family may use different ov dd and v dd input levels. int 188 l1_tstclk (1) 204 l2_tstclk (1) 203 lssd_mode (1) 205 mcp 186 pll_cfg[0-3] 213, 211, 210, 208 qack 235 qreq 31 rsrv 232 smi 187 sreset 189 sysclk 212 ta 155 tben 234 tbst 192 tc[0-1] 224, 223 tck 201 tdi 199 tdo 198 tea 154 tlbisync 233 tms 200 trst 202 ts 149 tsiz[0-2] 197, 196, 195 tt[0-4] 191, 190, 185, 184, 180 wt 236 nc table 7. signal pinout listing (continued) signal name cerquad pin number
19 tspc603r 5410a?hirel?10/04 table 8. address and data bus signal index for cerquad, cbga 255 and ci-cga 255 packages signal name abbreviation signal function signal type address bus a[0-31] if output, physical address of data to be transferred if input, represents the physical address of a snoop operation i/o data bus dh[0-31] represents the state of data, during a data write operation if output, or during a data read operation if input i/o data bus dl[0-31] represents the state of data, during a data write operation if output, or during a data read operation if input i/o table 9. signal index for cerquad, cbga 255 and ci-cga 255 packages signal name abbreviation signal function signal type address acknowledge aack the address phase of a transaction is complete input address bus busy abb if output, the 603r is the address bus master if input, the address bus is in use i/o address bus parity ap[0-3] if output, represents odd parity for each of 4 bytes of the physical address for a transaction if input, represents odd parity for each of 4 bytes of the physical address for snooping operations i/o address parity error ape incorrect address bus parity detected on a snoop output address retry artry if output, detects a condition in which a snooped address tenure must be retried if input, must retry the preceding address tenure i/o bus grant bg may, with the proper qualification, assu me mastership of the address bus input bus request br request mastership of the address bus output cache inhibit cl a single-beat transfer will not be cached output checkstop input ckstp_in must terminate operation by internally gating off all clocks, and release all outputs input checkstop output ckstp_out has detected a checkstop condition and has ceased operation output cache set entry cse[0-1] cache replacement set element for the current transaction reloading into or writing out of the cache output data bus busy dbb if output, the 603r is the data bus master if input, another device is bus master i/o data bus disable dbdis (for a write transaction) must release data bus and the data bus parity to high impedance during the following cycle input data bus grant dbg may, with the proper qualification, a ssume mastership of the data bus input data bus write only dbw0 may run the data bus tenure input data bus parity dp[0-7] if output, odd parity for each of 8 bytes of data write transactions if input, odd parity for each byte of read data i/o data parity error dpe incorrect data bus parity output data retry drtry must invalidate the data from the previous read operation input
20 tspc603r 5410a?hirel?10/04 global gbl if output, a transaction is global if input, a transaction must be snooped by the 603r i/o hard reset hreset initiates a complete hard reset operation input interrupt int initiates an interrupt if bit ee of msr register is set input factory test lssd_mode lssd test control signal for factory use only input l1_tstclk lssd test control signal for factory use only input l2_tstclk lssd test control signal for factory use only input machine check interrupt mcp initiates a machine check interrupt operat ion if the bit me of msr register and bit emcp of hid0 register are set input pll configuration pll_cfg[0-3] configures the operation of the pll and the internal processor clock frequency input power supply indicator voltdetgnd available only on bga package indicates to the power supply that a low-voltage processor is present. output quiescent acknowledge qack all bus activity has terminated and the 603r may enter a quiescent (or low power) state input quiescent request qreq is requesting all bus activity normally to enter a quiescent (low power) state output reservation rsrv represents the state of the reservation coherency bit in the reservation address register output system management interrupt smi initiates a system management interrupt oper ation if the bit ee of msr register is set input soft reset sreset initiates processing for a reset exception input system clock sysclk represents the primary clock input for the 603r, and the bus clock frequency for 603r bus operation input test clock clk_out provides pll clock output for pll testing and monitoring output transfer acknowledge ta a single-beat data transfer completed successfully or a data beat in a burst transfer completed successfully input timebase enable tben the timebase should continue clocking input transfer burst tbst if output, a burst transfer is in progress if input, when snooping for single-beat reads i/o transfer code tc[0-1] special encoding for the transfer in progress output test clock tck clock signal for the ieee p1149.1 test access port (tap) input test data input tdi serial data input for the tap input test data output tdo serial data output for the tap output transfer error acknowledge tea a bus error occurred input tlbi sync tlbisync instruction execution should stop after execution of a tlbsync instruction input test mode select tms selects the principal operations of the test-support circuitry input test reset trst provides an asynchronous reset of the tap controller input transfer size tsiz[0-2] for memory accesses, these signals along with tbst indicate the data transfer size for the current bus operation i/o table 9. signal index for cerquad, cbga 255 and ci-cga 255 packages (continued) signal name abbreviation signal function signal type
21 tspc603r 5410a?hirel?10/04 electrical characteristics general requirements all static and dynamic electrical characterist ics specified for inspection purposes and the relevant measurement conditions are given below: table 10: static electrical characteristics for the electrical variants table 11: dynamic electrical characteristics for the 603r the processor core frequency is determined by the bus (sysclk) frequency and the settings of the pll_cfg0 to pll_cfg3 signals. all timings are respectively specified to the rising edge of sysclk. these specifications are for 166 mhz to 300 mhz processor core frequencies for cbga 255 and ci-cga 255 packages and 166 mhz to 200 mhz processor core frequencies for the cerquad 240 package. static characteristics notes: 1. excludes test signals (lssd_mode, l1_tstclk, l2_tstclk, and jtag signals) 2. capacitance is periodically sampled rather than 100% tested 3. leakage currents are measured for nominal ov dd and v dd or both ov dd and v dd . same variation (for example, both v dd and ov dd vary by either +5% or -5%) transfer start ts if output, begun a memory bus transaction and the address bus and transfer attribute signals are valid if input, another master has begun a bus transaction and the address bus and transfer attribute signals are valid for snooping (see gbl ) i/o transfer type tt[0-4] type of transfer in progress i/o write-through wt a single-beat transaction is write-through output table 9. signal index for cerquad, cbga 255 and ci-cga 255 packages (continued) signal name abbreviation signal function signal type table 10. electrical characteristics with v dd = a v dd = 2.5v 5%; o v dd = 3.3 5%v, gnd = 0v, -55c t c 125c characteristics symbol min max unit input high voltage (all inputs except sysclk) v ih 25.5 v input low voltage (all inputs except sysclk) v il gnd 0.8 v sysclk input high voltage cv ih 2.4 5.5 v sysclk input low voltage cv il gnd 0.4 v input leakage current v in = 3.465v (1)(3) i in -30a v in = 5.5v (1)(3) i in - 300 a hi-z (off-state) leakage current v in = 3.465v (1)(3) i tsi -30a v in = 5.5v (1)(3) i tsi - 300 a output high voltage i oh = -7 ma v oh 2.4 - v output low voltage i ol = +7 ma v ol -0.4 v capacitance, v in = 0v, f = 1 mhz (2) (excludes ts , abb , dbb , and artry )c in -10pf capacitance, v in = 0v, f = 1 mhz (2) (for ts , abb , dbb , and artry )c in -15pf
22 tspc603r 5410a?hirel?10/04 dynamic characteristics clock ac specifications table 11 provides the clock ac timing specifications as defined in figure 6. notes: 1. rise and fall times for the sysclk input are measured from 0.4v to 2.4v 2. cycle-to-cycle jitter is guaranteed by design 3. timing is guaranteed by design and characterization and is not tested 4. the pll relock time is the maximum amount of time required for pll lock after a stable v dd , ov dd , av dd and sysclk are reached during the power-on reset sequence. this specification also applies when the pll has been disabled and subse- quently re-enabled during sleep mode. also note that hreset must be held asserted for a minimum of 255 bus clocks after the pll relock time (100 s) during the power-on reset sequence. 5. caution : the sysclk frequency and pll_cfg[0-3] settings must be chosen so that the resulting sysclk (bus) fre- quency, cpu (core) frequency, and pll (vco) frequency do not exceed their respective maximum or minimum operating frequencies. refer to the pll_cfg[0-3] signal description for valid pll_cfg[0-3] settings. figure 6. sysclk input timing diagram table 11. clock ac timing specifications (1)(2)(3)(4) with v dd = a v dd = 2.5v 5%; o v dd = 3.3 5%v, gnd = 0v, -55 c t c 125 c figure number characteristics cbga 255, ci-cga 255 and cerquad cbga 255 and ci-cga 255 166 mhz 200 mhz 233 mhz 266 mhz 300 mhz unit note min max min max min max min max min max processor frequency 150 166 150 200 180 233 180 266 180 300 mhz (5) vco frequency 300 332 300 400 360 466 360 532 360 600 mhz (5) sysclk (bus) frequency 25 66.7 33.3 66.7 33.3 75 33.3 75 33.3 75 mhz (5) 1 sysclk cycle time 15 30 13.3 30 13.3 30 13.3 30 13.3 30 ns 2,3 sysclk rise and fall time ?2?2?2?2?2ns (1) 4 sysclk duty cycle (1.4v measured) 40 60 40 60 40 60 40 60 40 60 % (3) sysclk jitter ? 150 ? 150 ? 150 ? 150 ? 150 ps (2) 603r internal pll relock time ? 100 ? 100 ? 100 ? 100 ? 100 s (3)(4) vm cvil cvih sysclk 2 3 vm = midpoint voltage (1.4v) 1 vm vm
23 tspc603r 5410a?hirel?10/04 input ac specifications table 12 provides the input ac timing specific ations for the 603r as defined in figure 7 and figure 8. notes: 1. all input specifications are measured from the ttl level (0 .8 or 2v) of the signal in ques tion to the 1.4v of the risin g edge of the input sysclk. both input and output timing s are measured at the pin. see figure 8. 2. address/data/transfer attribute input signals are composed of the following: a[0-31], ap[0-3], tt[0-4], tc[0-1], tbst , tsiz[0-2], gbl , dh[0-31], dl[0-31], dp[9-7]. 3. all other input signals are composed of the following: ts , abb , dbb , artry , bg , aack , dbg , dbwo , ta , drtry , tea , dbdis , hreset , sreset , int , smi , mcp , tben, qack , tlbisync . 4. the setup and hold time is with respect to the rising edge of hreset . see figure 8. 5. t sysclk is the period of the external clock (sysclk) in nanosecon ds (ns). the numbers given in the table must be multiplied by the period of sysclk to compute the actual time durati on (in nanoseconds) of t he parameter in question. 6. these values are guaranteed by design, and are not tested. 7. this specification is for configur ation mode only. al so note that hreset must be held asserted for a minimum of 255 bus clocks after the pll relock time (100 s) during the power-on reset sequence. figure 7. input timing diagram table 12. input ac timing specifications (1) with v dd = a v dd = 2.5v 5%; o v dd = 3.3 5%v, gnd = 0v, -55 c t c 125 c figure number characteristics cbga 255, ci-cga 255 and cerquad 240 packages cbga 255 and ci-cga 255 unit note 166, 200 mhz 233, 266 mhz 300 mhz min max min max min max 10a address/data/transfer attribute inputs valid to sysclk (input setup) 2.5 ? 2.5 ? 2.5 ? ns (2) 10b all other inputs valid to sysclk (input setup) 4 ? 3.5 ? 3.5 ? ns (3) 10c mode select inputs valid to hreset (input setup) (for drtry , qack and tlbisync ) 8?8?8? t syscl k (4)(5)(6 )(7) 11a sysclk to address/data/transfer attribute inputs invalid (input hold) 1?1?1?ns (2) 11b sysclk to all other inputs invalid (input hold) 1 ? 1 ? 1 ? ns (3) 11c hreset to mode select inputs invalid (input hold) (for drtry , qack , and tlbisync ) 0?0?0?ns (4)(6) (7) vm sysclk all inputs vm = midpoint voltage (1.4v) 10a 10b 11a 11b
24 tspc603r 5410a?hirel?10/04 figure 8. mode select input timing diagram output ac specifications table 13 provides the output ac timing specifications for the 603r (shown in figure 9). notes: 1. all output specifications are measured from the 1.4v of the rising edge of sysclk to the ttl level (0.8v or 2v) of the signal in question. both input and output timing s are measured at the pin. see figure 9. 2. all maximum timing specifications assume c l = 50 pf. mode pins hreset 10c 11c vm = midpoint voltage (1.4v) vm table 13. output ac timing specifications (1)(2) with v dd = a v dd = 2.5v 5%; o v dd = 3.3 5%v, gnd = 0v, c l = 50 pf, 55c t c 125c number characteristics cbga 255, ci-cga 255 and cerquad 240 packages cbga 255 and ci-cga 255 unit note 166, 200 mhz 233, 266 mhz 300 mhz min max min max min max 12 sysclk to output driven (output enable time) 1?1?1?ns 13a sysclk to output valid (5.5v to 0.8v ? ts , abb , artry , dbb ) ?9?9?9ns (4) 13b sysclk to output valid (ts , abb , artry , dbb ) ?8?8?8ns (6) 14a sysclk to output valid (5.5v to 0.8v ? all except ts , abb , artry , dbb ) ?11?11?11ns (4) 14b sysclk to output valid (all except ts , abb , artry , dbb ) ?9?9?9ns (6) 15 sysclk to output invalid (output hold) 1 ? 1 ? 1 ? ns (3) 16 sysclk to output high impedance (all except artry , abb , dbb ) ?8.5?8?8ns 17 sysclk to abb , dbb , high impedance after precharge ?1?1?1t sysclk (5)(7) 18 sysclk to artry high impedance before precharge ?8?7.5?7.5ns 19 sysclk to artry precharge enable 0.2 t sysclk + 1 ? 0.2 t sysclk + 1 ? 0.2 t sysclk ?ns (3)(5) (8) 20 maximum delay to artry precharge ? 1 ? 1 ? 1 t sysclk (5)(8) 21 sysclk to artry high impedance after precharge ?2?2?2t sysclk (6)(8)
25 tspc603r 5410a?hirel?10/04 3. this minimum parameter assumes c l = 0 pf. 4. sysclk to output valid (5.5v to 0.8v) incl udes the extra delay associated with disch arging the external voltage from 5.5v to 0.8v instead of from v dd to 0.8v (5v cmos levels instead of 3.3v cmos levels). 5. t sysclk is the period of the external bus clock (sysclk) in nanos econds (ns). the numbers given in the table must be multi- plied by the period of sysclk to compute the actual time duration (ns) of the parameter in question. 6. the output signal transitions from gnd to 2v or v dd to 0.8v. 7. the nominal precharge width for abb and dbb is 0.5 t sysclk . 8. the nominal precharge width for artry is 1 t sysclk . figure 9. output timing diagram sysclk 12 14 13 15 16 ts ar tr y abb , dbb vm vm vm = midpoint voltage (1.4v) vm 13 20 18 17 21 19 15 16 all outputs (except ts , abb , dbb , artry )
26 tspc603r 5410a?hirel?10/04 jtag ac timing specifications notes: 1. trst is an asynchronous signal. the setup time is for test purposes only. 2. non-test signal input ti ming with respect to tck. 3. non-test signal output timing with respect to tck. figure 10. clock input timing diagram figure 11. trst timing diagram table 14. jtag ac timing specificati ons (independent of sysclk); v dd = a v dd = 2.5v 5%; o v dd = 3.3 5%v, gnd = 0v, c l = 50 pf, -55 c t c 125 c number characteristics min max unit notes tck frequency of operation 0 16 mhz 1 tck cycle time 62.5 ? ns 2 tck clock pulse width measured at 1.4v 25 ? ns 3 tck rise and fall times 0 3 ns 4 trst setup time to tck rising edge 13 ? ns (1) 5 trst assert time 40 ? ns 6 boundary scan input data setup time 6 ? ns (2) 7 boundary scan input data hold time 27 ? ns (2) 8 tck to output data valid 4 25 ns (3) 9 tck to output high impedance 3 24 ns (3) 10 tms, tdi data setup time 0 ? ns 11 tms, tdi data hold time 25 ? ns 12 tck to tdo data valid 4 24 ns 13 tck to tdo high impedance 3 15 ns tck 2 2 1 vm vm vm 3 3 vm = midpoint voltage (1.4v) 4 5 trst tck vm
27 tspc603r 5410a?hirel?10/04 figure 12. boundary-scan timing diagram figure 13. test access port timing diagram functional description powerpc registers and programming model the powerpc architecture defines register-to-register operations for most computa- tional instructions. source operands for these instructions are accessed from the registers or are provided as immediate values embedded in the instruction opcode. the three-register instruction format allows specification of a target register distinct from the two source operands. load and store instructions transfer data between registers and memory. powerpc processors have two levels of privilege?supervisor mode of operation (typi- cally used by the operating system) and user mode of operation (used by the application software). the programming models incor porate 32 gprs, 32 fprs, special-purpose registers (sprs) and several miscellaneous registers. each powerpc microprocessor also has its own unique set of hardware implementation (hid) registers. tck data inputs data outputs data outputs data outputs 6 7 8 8 9 vm vm output data valid output data valid input data valid tck tdi, tms tdo tdo tdo 12 13 vm vm 10 11 output data valid output data valid input data valid 12
28 tspc603r 5410a?hirel?10/04 having access to privilege in structions, registers, and other resources allows the operat- ing system to control the application environment (providing virtual memory and protecting operating system and critical machine resources). in structions that control the state of the processor, the address translation mechanism, and supervisor registers can be executed only when the processor is operating in supervisor mode. the following sections summarize the powe rpc registers that are implemented in the 603r. general-purpose registers (gprs) the powerpc architecture defines 32 user-level, general-purpose registers (gprs). these registers are either 32 bits wide in 32-bit powerpc microprocessors or 64 bits wide in 64-bit powerpc microprocessors. the gprs serve as the data source or desti- nation for all integer instructions. floating-point registers (fprs) the powerpc architecture also defines 32 us er-level, 64-bit floating-point registers (fprs). the fprs serve as the data source or destination for floating-point instructions. these registers can contain data objects of either single- or double-precision float- ing-point formats. condition register (cr) the cr is a 32-bit user-level register that cons ists of eight four-bit fields that reflect the results of certain operations, such as move, integer and floating-point compare, arith- metic, and logical instructions, and provide a mechanism for testing and branching. floating-point status and control register (fpscr) the floating-point status and control register (fpscr) is a user-level register that contains all exception signal bits, exception summary bits, exception enable bits, and rounding control bits needed for compliance with the ieee 754 standard. machine state register (msr) the machine state register (msr) is a supervisor-level register that defines the state of the processor. the contents of this register are saved when an exception is taken and restored when the exception handling is completed. the 603r implements the msr as a 32-bit register, 64-bit powerpc processors implement a 64-bit msr. segment registers (srs) for memory management, 32-bit powerpc microprocessors implement sixteen 32-bit segment registers (srs). to speed access, the 603r implements the segment regis- ters as two arrays; a main array (for data memory accesses) and a shadow array (for instruction memory accesses). loading a segment entry with the move to segment register (stsr) instruction loads both arrays.
29 tspc603r 5410a?hirel?10/04 special-purpose registers (sprs) the powerpc operating environment architecture defines numerous special-purpose registers that serve a variety of functions, such as providing controls, indicating status, configuring the processor, and performing special operations. during normal execution, a program can access the registers, shown in figure 14 on page 31, depending on the program?s access privilege (supervisor or user, determined by the privilege-level (pr) bit in the msr. note that registers such as the gprs and fprs are accessed through operands that are part of the instructions. acce ss to registers can be explicit (that is, through the use of specific instructions for that purpose such as move to special-pur- pose register ( mtspr ) and move from special-purpose register ( mfspr ) instructions or implicit, as the part of the execution of an instruction. some registers are accessed both explicitly and implicitly. in the 603r, all sprs are 32 bits wide. user-level sprs: the following 603r sprs are accessible by user-level software: ? link register (lr) - the link register can be used to provide the branch target address and to hold the return address after branch and link instructions. the lr is 32 bits wide in 32-bit implementations. ? count register (ctr) - the crt is decremented and tested automatically as a result of branch-and-count instructions. the ctr is 32 bits wide in 32-bit implementations. ? integer exception register (xer) - the 32-bit xer contains the summary overflow bit, integer carry bit, overflow bit, and a field specifying the number of bytes to be transferred by a load string word indexed (lswx) or store string word indexed (stswx) instruction. supervisor-level sprs: the 603r also contains sprs that can be accessed only by supervisor-level software. these registers consist of the following: ? the 32-bit dsisr defines the cause of data access and alignment exceptions. ? the data address register (dar) is a 32-bit register that holds the address of an access after an alignment or dsi exception. ? decrementer register (dec) is a 32-bit decrementing counter that provides a mechanism for causing a decrementer exception after a programmable delay. ? the 32-bit sdr1 specifies the page table format used in virtual-to-physical address translation for pages. (note that physical address is referred to as real address in the architecture specification). ? the machine status save/restore register 0 (srr0) is a 32-bit register that is used by the 603r for saving the address of the instruction that caused the exception, and the address to return to when a return from interrupt ( rfi ) instruction is executed. ? the machine status save/restore register 1 (srr1) is a 32-bit register used to save machine status on exceptions and to restore machine status when an rfi instruction is executed. ? the 32-bit sprg0-sprg3 registers are provided for operating system use. ? the external access register (ear) is a 32-bit register that controls access to the external control fa cility through the external control in word indexed ( eciwx ) and external control out word indexed ( ecowx ) instructions.
30 tspc603r 5410a?hirel?10/04 ? the time base register (tb) is a 64-bit register that maintains the time of day and operates interval timers. the tb consists of two 32-bit fields - time base upper (tbu) and time base lower (tbl). ? the processor version register (pvr) is a 32-bit, read-only register that identifies the version (model) and revision level of the powerpc processor. ? block address translation (bat) arrays - the powerpc architecture defines 16 bat registers, divided into four pairs of data bats (dbats) and four pairs of instruction bats (ibats). see figure 14 for a list of the spr numbers for the bat arrays. the following supervisor-level sprs are implementation-specific to the 603r: ? the dmiss and imiss registers are read-only registers that are loaded automatically upon an instruction or data tlb miss. ? the hash1 and hash2 registers contain the physical addresses of the primary and secondary page table entry groups (ptegs). ? the icmp and dcmp registers contain a duplicate of the first word in the page table entry (pte) for which the table search is looking. ? the required physical address (rpa) register is loaded by the processor with the second word of the correct pte during a page table search. ? the hardware implementation (hid0 and hid1) registers provide the means for enabling the 603r?s checkstops and features, and allows software to read the configuration of the pll configuration signals. ? the instruction address breakpoint register (iabr) is loaded with an instruction address that is compared to instruction addresses in the dispatch queue. when an address match occurs, an instruction address breakpoint exception is generated. figure 14 shows all the 603r registers avail able at the user and supervisor level. the number to the right of the sprs indicate the number that is used in the syntax of the instruction operands to access the register.
31 tspc603r 5410a?hirel?10/04 figure 14. powerpc microprocessor programming model ? register user model general-purpose registers gpr0 gpr1 gpr31 fpr0 fpr1 cr gpr31 floating-point registers condition register xer xer lr ctr tbl tbu fpscr link register count register floating-point status and control register spr1 spr8 spr9 time base facility (for reading) tbr 268 tbr 269 supervisor model hardware implementation registers (1) hid0 hid1 instruction bat registers ibat0u ibat0l ibat1u ibat1l ibat2u ibat2l ibat3u ibat3l spr 528 spr1 008 spr1 009 spr 529 spr 530 spr 531 spr 532 spr 533 spr 534 spr 535 spr 536 spr 537 spr 538 spr 539 spr 540 spr 541 spr 542 spr 543 spr 976 spr 977 spr 978 spr 979 spr 980 spr 981 spr 982 spr 25 sdr1 sdr1 miscellaneous registers data bat registers dbat0u dbat0l dbat1u dbat2u dbat1l dbat2l dbat3l dbat3u software table search registers (1) segment registers dmiss dcmp hash1 hash2 imiss icmp rpa sr0 sr1 sr 15 data address register dsisr dar sprgs save and restore sprg0 sprg1 sprg2 sprg3 msr machine state register pvr processor version register configuration registers spr 287 memory management registers exception handling registers spr 19 dsisr spr 18 decrementer dec spr 22 srr0 spr 26 srr1 spr 27 spr 272 spr 273 spr 274 spr 275 time base facility (for writing) tbl spr 284 tbu spr 285 instruction address breakpoint register (1) iabr spr 1010 external address register (optional) ear spr 282
32 tspc603r 5410a?hirel?10/04 instruction set and addressing modes the following subsections describe the powerpc instruction set and addressing modes in general. powerpc instruction set and addressing modes all powerpc instructions are encoded as single-word (32-bit) opcodes. instruction for- mats are consistent among all instruction types, permitting efficient decoding to occur in parallel with operand accesses. this fixed instruction length and consistent format greatly simplifies in struction pipelining. powerpc instruction set the powerpc instructions are divid ed into the following categories: integer instructions ? these include computational and logical instructions ? integer arithmetic instructions ? integer compare instructions ? integer logical instructions ? integer rotate and shift instructions floating-point instructions ? these include floating-point computational instructions, as well as instructions that affect the fpscr ? floating-point arit hmetic instructions ? floating-point multip ly/add instructions ? floating-point rounding and conversion instructions ? floating-point compare instructions ? floating-point status and control instructions load/store instructions ? these include integer and floating-point load and store instructions ? integer load and store instruction ? integer load and store multiple instructions ? floating-point load and store ? primitives used to construct atomic memory operations ( lwarx and stwcx instructions) flow control instructions ? these include branching instructions, condition register logical instructions, trap instructions, and other instructions that affect the instruction flow ? branch and trap instructions ? condition register logical instructions processor control instructions ? these instructions are used for synchronizing memory accesses and management of caches, tlbs, and the segment registers ? move to/from spr instructions ? move to/from msr ? synchronize ? instruction synchronize memory contro l instructions ? these instructions provide control of caches, tlbs, and segment registers ? supervisor-level cache management instructions ? user-level cache instructions ? segment register manipulation instructions ? translation lookaside buffer management instructions
33 tspc603r 5410a?hirel?10/04 note that this grouping of the instructions does not indicate which execution unit exe- cutes a particular instruction or group of instructions. integer instructions operate on byte, half-word, and word operands. floating-point instructions operate on single-precision (one word) and double-precision (one double word) floating-point operands. the powerpc architecture uses instructions that are four bytes long and word-aligned. it provides for byte, half-word, and word operand loads and stores between the memory and a set of 32 gprs. it also provides for word and double-word operand loads and stores between the memory and a set of 32 float- ing-point registers (fprs). computational instructions do not modify the memory. to use a memory operand in a computation and then modify the same or another memory location, the memory con- tents must be loaded into a register, modified, and then written back to the target location with distinct instructions. powerpc processors follow the program flow when they are in the normal execution state. however, the flow of instructions can be interrupted directly by the execution of an instruction or by an asynchronous event. eith er kind of exception may cause one of sev- eral components of the syste m software to be invoked. calculating effective address the effective address (ea) is the 32-bit address computed by the processor when executing a memory access or branch instruction or when fetching the next sequen- tial instruction. the powerpc architecture supports two simple memory addressing modes: ? ea = (ra|0) + offset (including offset = 0) (register indirect with immediate index) ? ea = (ra|0) + rb (register indirect with index) these simple addressing modes allow efficient address generation for memory accesses. calculation of the effective address for aligned transfers occurs in a single clock cycle. for a memory access instruction, if the sum of the effective address and the operand length exceeds the maximum effective addres s, the memory operand is considered to wrap around from the maximum effective address to effective address 0. effective address computations for both data and instruction accesses use 32-bit unsigned binary arithmetic. a carry over from bit 0 is ignored in 32-bit implementations.
34 tspc603r 5410a?hirel?10/04 powerpc 603r microprocessor instruction set the 603r instruction set is defined as follows: the 603r provides hardware support for all 32-bit powerpc instructions. the 603r provides two implementation-specific instructions used for software table search operations following tlb misses: ? load data tlb entry ( tlbld ) ? load instruction tlb entry ( tlbli ) the 603r implements the following instructions which are defined as optional by the powerpc architecture : ? external control in word indexed ( eciwx ) ? external control out word indexed ( ecowx ) ? floating select ( fsed ) ? floating reciprocal estimate single-precision ( fres ) ? floating reciprocal square root estimate ( frsqrte ) ? store floating-point as integer word ( stfiwx ) cache implementation the following subsections describe the way the powerpc architecture deals with cache in general, and the 603r?s specific implementation. powerpc cache characteristics the powerpc architecture does not define hardware aspects of cache implementations. for example, some powerpc processors, including the 603r, have separate instruction and data caches (harvard architecture). the powerpc microprocessor controls the following memory access modes on a page or block basis: write-back/write-through mode cache-inhibited mode memory coherency note that in the 603r, a cache line is defined as eight words. the vea defines cache management instructions that provide a means by which the application programmer can affect the cache contents. powerpc 603r microprocessor cache implementation the 603r has two 16-kbyte, four-way set-associative (instruction and data) caches. the caches are physically addressed, and the data cache can operate in either write-back or write-through modes as specified by the powerpc architecture. the data cache is configured as 128 sets of four lines each. each line consists of 32 bytes, two state bits, and an address tag. the two state bits implement the three-state mei (modified/exclusive/invalid) protocol. each line contains eight 32-bit words. note that the powerpc architecture defines the term block as the cacheable unit. for the 603r, the block size is equivalent to a cache line. a block diagram of the data cache organization is shown in figure 15 on page 35. the instruction cache also consists of 128 sets of 4 lines, and each line consists of 32 bytes, an address tag, and a valid bit. the instruction cache may not be written to except through a line fill operation. the instruction cache is not snooped, and cache coherency must be maintained by software. a fast hardware in validation capability is provided to support cache maintenance. the organization of the instruction cache is very similar to the data cache shown in figure 15 on page 35.
35 tspc603r 5410a?hirel?10/04 each cache line contains eight contiguous words from memory that are loaded from an 8-word boundary (that is, bits a27-a32 of the effective addresses are zero); thus, a cache line never crosses a page boundary. misaligned accesses across a page bound- ary can incur a performance penalty. the 603?s cache lines are loaded in four beats of 64 bits each. the burst load is per- formed as ?critical double word first?. the cache that is being loaded is blocked to internal accesses until the load is completed. the critical double word is simultaneously written to the cache and forwarded to the requesting unit, thus minimizing stalls due to load delays. to ensure coherency among caches in a mult iprocessor (or multiple caching device) implementation, the 603r implemements the mei protocol. these three states, modi- fied, exclusive, and invalid, indicate the state of the cache block as follows: modified - the cache line is modified with respect to system memory; that is, data for this address is valid only in the cache and not in the system memory exclusive - this cache line holds valid data th at is identical to the data at this address in-system memory. no other cache has this data invalid - this cache line does not hold valid data cache coherency is enforced by on-chip bus snooping logic. since the 603r?s data cache tags are single ported, a simultaneous load or store and snoop access represent a resource contention. the snoop access is granted first access to the tags. the load or store then occurs on the clock following snoop. figure 15. data cache organization exception model the following subsections describe the powerpc exception model and the 603r implementation. powerpc exception model the powerpc exception mechanism allows the processor to change to supervisor state as a result of external singles, errors, or unusual conditions arisin g in the execution of instructions, and differ from the arithmetic exceptions defined by the ieee for float- ing-point operations. when exceptions occur, information about the state of the processor is saved to certain registers and the processor begins execution at an address (exception vector) predetermined for each exception. processing of exceptions occurs in supe rvisor mode. block 0 state state state state address tag 0 address tag 1 address tag 2 address tag 3 block 1 block 2 block 3 words 0-07 words 0-07 words 0-07 words 0-07 8 words/block 128 sets
36 tspc603r 5410a?hirel?10/04 although multiple exception conditions can map to a single exception vector, a more specific condition may be determined by examining a register associated with the exception - for example, the dsisr and the fpscr. additionally, some exception con- ditions can be explicitly enabled or disabled by software. the powerpc architecture requires that exceptions be handled in program order; there- fore, although a particular implementation ma y recognize exception conditions out of order, they are presented strictly in order. when an instruction-caused exception is rec- ognized, any unexecuted instructions that appear earlier in the instruction stream, including any that have not yet entered the execute state, must be completed before the exception is taken. any exceptions caused by such instructions are handled first. like- wise, exceptions that are asynchronous and precise are recognized when they occur, but are not handled until the instruction currently in the completion state successfully completes execution or generates an exception, and the completed store queue is emptied. unless a catastrophe event causes a system reset or machine check exception, only one exception is handled at a time. if, for example, a single instruction encounters multi- ple exception conditions, those condit ions are encountered sequentially. after the exception handler handles an exception, the instruction execution continues until the next exception condition is encountered. however, in many cases there is no attempt to re-execute the instruction. this method of recognizing and handling excep- tion conditions sequentially guarantees that exceptions are recoverable. exception handlers should save the information stored in srr0 and srr1 early to pre- vent the program state from being lost due to a system reset and machine check exception or to an instruction-caused exception in the exception handler, and before enabling external interrupts. the powerpc architecture supports four types of exceptions: synchronous, precise ? these are caused by instructions. all instruction-caused exceptions are handled precisely; that is, the machine state at the time the exception occurs is known and can be completely restored. this means that (excluding the trap and system call exceptions) the address of the faulting instruction is provided to the exception handler and that neither the faulting instruction nor subseq uent instructions in the code stream will comp lete execution before the exception is taken. once the exception is processed, execution resumes at the address of the faulting instruction (or at an alternate address provided by the exception handler). when an exception is taken due to a trap or system call instruction, execution resumes at an address provided by the handler. synchronous, imprecise ? the powerpc architecture defines two imprecise floating-point exception modes, recoverable and nonrecoverable. even though the 603r provides a means to enable the imprecise modes, it implements these modes identically to the precise mode (that is, all enabled floating-point exceptions are always precise on the 603r). asynchronous, maskable ? the external, smi, and decrementer interrupts are maskable asynchronous exceptions. when these exceptions occur, their handling is postponed until the next instruction, and any exceptions associated with that instruction completes execution. if there are no instructions in the execution units, the exception is taken immediately upon determination of the correct restart address (for loading srr0).
37 tspc603r 5410a?hirel?10/04 asynchronous, non-maskable ? there are two non-maskable asynchronous exceptions: the system reset and machine check exception. these exceptions may not be recoverable, or may provide a limited degree of recoverability. all exceptions report recoverability th rough the smr[ri] bit. powerpc 603r microprocessor exception model as specified by the powerpc architecture, all 603r exceptions can be described as either precise or imprecise and either synchronous or asynchronous. asynchronous exceptions (some of which are maskable) are caused by events external to the proces- sor?s execution; synchronous exceptions, wh ich are all handled precisely by the 603r, are caused by instructions. the 603r ex ception classes are shown in table 15. although exceptions have other characteristics as well, such as whether they are maskable or non-maskable, the distinctions shown in table 15 define categories of exceptions that the 603r handles uniquely. note that table 15 includes no synchronous imprecise instructions. while the powerpc architecture supports imprecise handling of floating-point exceptions, the 603r implements these exception modes as precise exceptions. the 603r?s exceptions, and conditions that cause them, are listed in table 16. excep- tions that are specific to the 603r are indicated. table 15. powerpc 603r microprocessor exception classifications synchronous/asynchronous precise/imprecise exception type asynchronous, non maskable imprecise machine check system reset asynchronous, maskable precise external interrupt decrementer system management interrupt synchronous precise instruction-caused exceptions table 16. exceptions and conditions exception type vector offset (hex) causing conditions reserved 00000 ? system reset 00100 a system reset is caused by the assertion of either sreset or hreset machine check 00200 a machine check is caused by the assertion of the tea signal during a data bus transaction, assertion of mcp, or an address or data parity error dsi 00300 the cause of a dsi exception can be determined by the bit settings in the dsisr, listed as follows: 1 set if the translation of an attempted access is not found in the primary hash table entry group (hteg), or in the rehashed secondary hteg , or in the range of the dbat register; otherwise cleared 4 set if a memory access is not permitted by the page or dbat protection mechanism; otherwise cleared 5 set by an eciwx or ecowx instruction if the access is to an address that is marked as write-through, or execution of a load/store instruction that accesse s a direct-store segment 6 set for a store operation and cleared for a load operation 11 set if eciwx or ecowx is used and ear[e] is cleared
38 tspc603r 5410a?hirel?10/04 isi 00400 an isi exception is caused when an instruction fetch cannot be performed for any of the following reasons: the effective (logical) address cannot be tran slated. that is, there is a page fault for this portion of the translation, so an isi exception must be taken to load the pte (and possibly the page) into memory the fetch access violates memory protection. if the key bits (ks and kp) in the segment register and the pp bits in the pte are set to prohibit read access, instructions cannot be fetched from this location external interrupt 00500 an external interrupt is caused when msr[ee] = 1 and the int signal is asserted alignment 00600 an alignment exception is caused when the 603e cannot perform a memory access for any of the reasons described below: the operand of a floating-point load or store instruction is not word-aligned the operand of lmw , stmw , lwarx , and stwcx , instructions are not aligned the operand of a single-register load or st ore operation is not aligned, and the 603e is in little-endian mode the instruction is lmw , stmw , lswi , lwsx , stswi , stswx and the 603e is in little-endian mode the operand of dcbz is in storage that is write-through-required, or caching inhibited program 00700 a program exception is caused by one of the following exception conditions, which correspond to bit settings in srr1 and arise during execution of an instruction: floating-point enabled exception ? a floa ting-point enabled exception condition is generated when the following condition is met: (msr[fe0] | msr[fe1]) & fpscr[fex] is 1 fpser[fex] is set by the execution of a floating-point instruction that causes an enabled exception or by the execution of one of the ?move to fpscr? instructions that results in both an exception condition bit and its corresponding enable bit being set in the fpscr illegal instruction ? an illegal instruct ion program exception is generated when execution of an instruction is attempted with an illegal opcode or illegal combination of opcode and extended opcode fields (includi ng powerpc instructions not implemented in the 603e), or when execution of an option al instruction not provided in the 603e is attempted (these do not include those optional instructions that are treated as no-ops) privileged instruction ? a privileged instru ction type program exception is generated when the execution of a privileged instructio n is attempted and the msr register user privilege bit, msr[pr], is set. in t he 603e, this exception is generated for mtspr or mfspr with an invalid spr field if spr[0] = 1 and msr[pr] = 1. this may not be true for all powerpc processors trap ? a trap type program exception is gener ated when any of the conditions specified in a trap instruction is met floating-point unavailable 00800 a floating-point unavailable exception is caused by an attempt to execute a floating-point instruction (including floating- point load, store, and more instructions) when the floating- point available bit is disabled, (msr[fp] = 0) decrementer 00900 the decrementer exception occurs when the most significant bit of the decrementer (dec) register transitions from 0 to 1. must also be enabled with the msr[ee] bit reserved 00a00?00bff ? system call 00c00 a system call exce ption occurs when a system ca ll (sc) instruction is executed trace 00d00 a trace execution is taken when msr[se] = 1 or when the currently completing instruction is a branch and msr[be] = 1 table 16. exceptions and conditions (continued) exception type vector offset (hex) causing conditions
39 tspc603r 5410a?hirel?10/04 memory management the following subsections describe the memo ry management features of the powerpc architecture, and the 603r implementation, respectively. powerpc memory management the primary functions of the mmu are to translate logical (effective) addresses to physi- cal addresses for memory accesses, and to provide access protection on blocks and pages of memory. there are two types of accesses generated by the 603r that require address translation ? instruction accesses, and data accesses to memory generated by load and store instructions. the powerpc mmu and exception model s upport demand-paged virtual memory. vir- tual memory management permits execution of programs larger than the size of physical memory; demand-paged implies that individual pages are loaded into physical memory from system memory only when t hey are first accessed by an executing program. the hashed page table is a variable-sized data structure that defines the mapping between virtual page numbers and physical page numbers. the page table size is a power of 2, and its starting address is a multiple of its size. the page table contains a number of page table entry groups (ptegs). a pteg con- tains eight page table entries (ptes) of eight bytes each; therefore, each pteg is 64 bytes long. pteg addresses are entry points for table search operations. address translations are enabled by setting bits in the msr-msr[ir] enables instruction address translations and msr[dr] enables data address translations. reserved 00e00 the 603e does not generate an exception to this vector. other powerpc processors may use this vector for floating-point assist exceptions reserved 00e10?00fff ? instruction translation miss 01000 an instruction translation miss exception is caused when an effective address for an instruction fetch cannot be translated by the itlb data load translation miss 01100 a data load translation miss exception is caused when an effective address for a data load operation cannot be translated by the dtlb data store translation miss 01200 a data store translation miss exception is caused when an effective address for a data store operation cannot be translated by the dtlb; or where a dtlb hit occurs, and the change bit in the pte must be set due to a data store operation instruction address breakpoint 01300 an instruction address breakpoint exception o ccurs when the address (bits 0-29) in the iabr matches the next instruction to complete in the completion unit, and the iabr enable bit (bit 30) is set to 1 system management interrupt 01400 a system management interrupt is ca used when msr[ee] = 1 and the smi input signal is asserted reserved 01500?02fff ? table 16. exceptions and conditions (continued) exception type vector offset (hex) causing conditions
40 tspc603r 5410a?hirel?10/04 powerpc 603r microprocessor memory management the instruction and data memory management units in the 603r provide 4 gbytes of logical address space accessible to the supervisor and user programs with a 4 kbyte page size and 256m byte segment size. block sizes range from 128 kbytes to 256 mbytes and are software selectable. in addition, the 603r uses an interim 52-bit virtual address and hashed page tables for generating 32-bit physical addresses. the mmus in the 603r rely on the exception processing mechanism for the implementation of the paged virtual memory environment and for enforcing protection of designated memory areas. instruction and data tlbs provide address translation in parallel with the on-chip cache access, incurring no additional time penalty in the event of a tlb hit. a tlb is a cache of the most recently used page table entries. the software is responsible for maintaining the consistency of the tlb with memory. the 603r?s tlbs are 64-entry, 2-way set-associative caches that contain instruction and data address translations. the 603r provides hardware assistance for software table search operations through the ashed page table on the tlb misses. the supervisor software can invalidate tlb entries selectively. the 603r also provides independent four-entry bat arrays for instructions and data that maintain address translations for blo cks of memory. these entries define blocks that can vary from 128 kbytes to 256 mbytes. the bat arrays are maintained by system software. as specified by the powerpc architecture, the hashed page table is a variable-sized data structure that defines the mappi ng between virtual page numbers and physical page numbers. the page table size is a power of 2, and its starting address is a multiple of its size. also as specified by the powerpc architecture, the page table contains a number of page table entry groups (ptegs). a pteg co ntains eight page table entries (ptes) of eight bytes each; therefore, each pteg is 64 bytes long. pteg addresses are entry points for table search operations. instruction timing the 603r is a pipelined superscalar processo r. a pipelined processor is one in which the processing of an instruction is reduced into discrete stages. because the processing of an instruction is broken into a series of stages, an instruction does not require the entire resources of an execution unit. for example, after an instruction completes the decode stage, it can pass on to the next stage, while the subsequent instruction can advance into the decode stage. this improves the throughput of the instruction flow. for example, it may take three cycles for a floating-point instruction to complete, but if there are no stalls in the floating-point pipeline, a series of floating-point instructions can have a throughput of one instruction per cycle. the instruction pipeline in the 603r has four major pipeline stages, described as follows: the fetch pipeline stage primarily involves retrieving instructions from the memory system and determining the location of the next instruction retrieval. additionally, the bpu decodes branches during the fetch stage and folds out branch instructions before the dispatch stage if possible. the dispatch pipeline stage is responsible for decoding the instructions supplied by the instruction retrieval stage, and determining which of the instructions are eligible to be dispatched in the current cycle. in addition, the source operands of the instructions are read from the appropriate register file and dispatched with the instruction to the execute pipeline stage. at the end of the dispatch pipeline stage, the dispatched instructions and their operands are latched by the appropriate execution unit.
41 tspc603r 5410a?hirel?10/04 during the execute pipeline stage each execution unit that has an executable instruction executes the selected instruction (perhaps over multiple cycles), writes the instruction?s result into the appropriate rename register, and notifies the completion stage when the instruction has finished execution. in the case of an internal exception, the execution unit reports the exception to the completion/writeback pipeline stage and discontinues instruction execution until the exception is handled. the exception is not signaled until that instruction is the next to be completed. execution of most floating-point instructions is pipelined within the fpu allowing up to three instructions to be executing in the fpu concurrently. the pipeline stages for the floating-point unit are multiply, add, and round-convert. execution of most load/store instructions is also pipelined. the load/store unit has two pipeline stages. the first stage is for effective address calculation and mmu translation and the second stage is for accessing the data in the cache. the complete/writeback pipeline stage ma intains the correct ar chitectural machine state and transfers the contents of the rename registers to the gprs and fprs as instructions are retired. if the completion logic detects an instruction causing an exception, all following instru ctions are cancelled, their execution results in rename registers are discarded, and instructions are fetched from the correct instruction stream. a superscalar processor is one that issues multiple independent instructions into multi- ple pipelines allowing instructions to execut e in parallel. the 603r has five independent execution units, one each for integer instructions, floating-point instructions, branch instructions, load/store instructions, and syst em register instructions. the iu and the fpu each have dedicated register files for maintaining operands (gprs and fprs, respectively), enabling integer calculations and floating-point calculations to occur simultaneously without interference. because the powerpc architecture can be applied to such a wide variety of implemen- tations, instruction timing among various powerpc processors varies accordingly.
42 tspc603r 5410a?hirel?10/04 preparation for delivery packaging microcircuits are prepared for delivery in accordance with mil-prf-38535. certificate of compliance atmel offers a certificate of compliance with each shipment of parts, affirming the prod- ucts are in compliance with the mil-std-883 standard and guaranteeing the parameters that are not tested at temperature extremes for the entire temperature range. handling mos devices must be handled with certain precautions to avoid damage caused by an accumulation of static charge. input pr otection devices have been designed in the chip to minimize the effect of this static buildup. however, the following handling practices are recommended: 1. the devices should be handled on benches with conductive and grounded surfaces 2. ground test equipment and tools should be used 3. the devices should not be handled by the leads 4. the devices should be stored in conductive foam or carriers 5. use of plastic, rubber, or silk in mos areas should be avoided 6. relative humidity above 50 percent should be maintained if practical
43 tspc603r 5410a?hirel?10/04 choice of clock relationships the 603r microprocessors provide customers with numerous clocking options. an inter- nal phase-lock loop synchronizes the proce ssor (cpu) clock to the bus or system clock (sysclk) at various ratios. inside each powerpc microprocessor is a phase-lock loop circuit. a voltage controlled oscillator (vco) is precisely controlled in frequency and phase by a frequency/phase detector which compar es the input bus frequency (sysclk frequency) to a submultiple of the vco. the ratio of cpu to sysclk freq uencies is often referred to as the bus mode (for exam- ple, 2:1 bus mode). in table 17, the horizontal scale represents th e bus frequency (sysclk) and the verti- cal scale represents the pll-cfg[0-3] signals. for a given sysclk (bus) frequen cy, the pll configuration si gnals set the internal cpu and vco frequency of operation. table 17. cpu frequencies for common bus frequencies and multipliers pll_cfg[0-3] cpu frequency in mhz (vco frequency in mhz) specific to cbga 255 and ci-cga 255 bus-to- core multiplier core-to vco multiplier bus 25 mhz bus 33.33 mhz bus 40 mhz bus 50 mhz bus 60 mhz bus 66.67 mhz bus 75 mhz 0100 2x 2x - - - - - - 150 (300) 0101 2x 4x - - - - - - - 0110 2.5x 2x - - - - 150 (300) 166 (333) 187 (375) 1000 3x 2x - - - 150 (300) 180 (360) 200 (400) 225 (450) 1110 3.5x 2x - - - 175 (350) 210 (420) 233 (466) 263 (525) 1010 4x 2x - - 160 (320) 200 (400) 240 (480) 267 (533) 300 (600) 0111 4.5x 2x - 150 (300) 180 (360) 225 (450) 270 (540) 300 (600) - 1011 5x 2x - 166 (333) 200 (400) 250 (500) 300 (600) -- 1001 5.5x 2x - 183 (366) 220 (440) 275 (550) --- 1101 6x 2x 150 (300) 200 (400) 240 (480) 300 (600) --- 0011 pll bypass 1111 clock off
44 tspc603r 5410a?hirel?10/04 notes: 1. some pll configurations may select bus, cpu or vco frequencies which are not supported. 2. in pll-bypass mode, the sysclk input signal clocks the internal processor directly, the pll is disabled, and the bus mode is set for 1:1 mode operation. this mode is intended for factory use only. the ac timing specifications given in this document do not apply in pll-bypass mode. 3. in clock-off mode, no clocking occurs inside the 603e regardless of the sysclk input. pll_cfg[0-3] cpu frequency in mhz (vco freque ncy in mhz) specific to cerquad bus-to-core multiplier core-to vco multiplier bus 25 mhz bus 33.33 mhz bus 40 mhz bus 50 mhz bus 60 mhz bus 66.67 mhz 0100 2x 2x ? ? ? ? ? ? 0101 2x 4x ? ? ? ? ? ? 0110 2.5x 2x ? ? ? ? 150 (300) 166 (333) 1000 3x 2x ? ? ? 150 (300) 180 (360) 200 (400) 1110 3.5x 2x ? ? ? 175 (350) ?? 1010 4x 2x ? ? 160 (320) 200 (400) ?? 0111 4.5x 2x ? 150 (300) 180 (360) ?? ? 1011 5x 2x ? 166 (333) 200 (400) ?? ? 1001 5.5x 2x ? 183 (366) ??? ? 1101 6x 2x 150 (300) 200 (400) ??? ? 0011 pll bypass 1111 clock off
45 tspc603r 5410a?hirel?10/04 system design information pll power supply filtering the a v dd power signal is implemented on the 603e to provide power to the clock gener- ation phase-locked loop. to ensure stability of the internal clock, the power supplied to the a v dd input signal should be filtered using a circuit similar to the one shown in figure 16. the circuit should be placed as close as possible to the a v dd pin to ensure it filters out as much noise as possible. the 0.1 f capacitor should be closest to the a v dd pin, followed by the 10 f capacitor, and finally the 10 ? resistor to v dd . these traces should be kept short and direct. figure 16. pll power supply filter circuit decoupling recommendations due to the 603e?s dynamic power managemen t feature, large address and data buses, and high operating frequencies, the 603e ca n generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. this noise must be prevented from reaching other components in the 603e system, and the 603e itself requires a clean, tightly regulated source of power. therefore, it is recom- mended that the system designer place at least one decoupling capacitor at each v dd and o v dd pin of the 603e. it is also recommended that these decoupling capacitors receive their power from separate v dd , o v dd , and gnd power planes in the pcb, utiliz- ing short traces to minimize inductance. these capacitors should vary in value from 220 pf to 10 f to provide both high and low frequency filtering, and should be placed as close as possible to their associated v dd or o v dd pin. the suggested values for the v dd pins are 220 pf (ceramic), 0.01 f (ceramic) and 0.1 f (ceramic). the suggested values for the o v dd pins are 0.01 f (ceramic), 0.1 f (ceramic), and 10 f (tantalum). only smt (surface mount technol- ogy) capacitors should be used to minimize lead inductance. in addition, it is recommended that there be several bulk storage capacitors distributed around the pcb, feeding the v dd and o v dd planes, to enable quick recharging of the smaller chip capacitors. these bulk capacito rs should also have a low esr (equivalent series resistance) rating to ensure the quick response time necessary. they should also be connected to the power and ground planes through two vias to minimize inductance. the suggested bulk capacito rs are 100 f (avx tps tant alum) or 330 f (avx tps tantalum). connection recommendations to ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. unused active low inputs should be tied to v dd . unused active high inputs should be connected to gnd. all nc (non-connected) signals must remain unconnected. power and ground connections must be made to all external v dd , o v dd , and gnd pins of the 603e. v dd av dd 0.1 f 10 f gnd 10?
46 tspc603r 5410a?hirel?10/04 pull-up resistor requirements the 603e requires high-resistive (weak: 10 k ? ) pull-up resistors on several control sig- nals of the bus interface to maintain the control signals in the negated state after they have been actively negated and released by the 603e or other bus master. these sig- nals are: ts , abb , dbb , and artry . in addition, the 603e has three open-drain style outputs that require pull-up resistors (weak or stronger: 4.7 k ? - 10 k ? ) if they are used by the system. these signals are: ape , dpe , and ckstp _out . during inactive periods on the bus, the address and transfer attributes on the bus are not driven by any master and may float in the high-impedance state for relatively long periods of time. since the 603e must contin ually monitor these signals for snooping, this floating condition may cause excessive power to be drawn by the input revivers on the 603e. it is recommended that these signals be pulled up through weak (10 k ? ) pull-up resistors or restored in some manner by the system. the snooped address and transfer attribute inputs are: a[0-3], ap[0-3], tt[0-4], tbst , and gbl . the data bus input receivers are normally turned off when no read operation is in progress and do not require pull-up resistors on the data bus. package mechanical data the following sections provide the package parameters and mechanical dimensions for the cbga and the cerquad packages. cbga package parameters the package parameters are as provided in the following list. the package type is 21 mm, 255-lead ceramic ball grid array (cbga). package outline 21 mm 21 mm interconnects 255 pitch 1.27 mm maximum module height 3 mm
47 tspc603r 5410a?hirel?10/04 mechanical dimensions of the cbga package figure 17 provides the mechanical dimensi ons and bottom surface nomenclature of the cbga package. figure 17. mechanical dimensions and bottom surface nomenclature of the cbga package ci-cga package parameters the package parameters are as provided in the following list. the package type is 21 mm, 255-lead ceramic ball grid array (ci-cga). package outline 21 mm 21 mm interconnects 255 pitch 1.27 mm typical module height 3.84 mm 0.200 f t 255x a 2x a1 corner p n 0.200 2x - e - 12345678910111213141516 a b c d e f g h j k l m n p r t e 0.300 t 0.150 d c h 0.150 t b - f - k k g s s s s - t - dim millimeters inches min max min max a 21.000 bsc 0.827 bsc b 21.000 bsc 0.827 bsc c 2.450 3.000 0.097 0.118 d 0.820 0.930 0.032 0.036 g 1.270 bsc 0.050 bsc h 0.790 0.990 0.031 0.039 k 0.635 bsc 0.025 bsc n 5.000 16.000 0.197 0.630 p 5.000 16.000 0.197 0.630 notes: 1. dimensioning and tolerancing per asme y14.5m - 1994 2. controlling dimension: millimeter
48 tspc603r 5410a?hirel?10/04 mechanical dimensions of the ci-cga package figure 18 provides the mechanical dimensi ons and bottom surface nomenclature of the ci-cga package. figure 18. mechanical dimensions and bottom surface nomenclature of the ci-cga package h v r c u notes: 1. dimensioning and tolerancing per asme y14.5m?1994 2. controlling dimension: millimeter 0.300 s s t t 0.150 s e s f 12345678910111213141516 t r p n m l k j h g f e d c b a g k k 255x d 0.150 t -t- a1 corner a 0.200 2x -e- p n b 0.200 2x -f- min max a b c d 0.790 0.990 g h 1.545 1.695 k n5.000 p7.000 r u v 0.25 0.35 dim 0.635 bsc 3.02 bsc 0.10 bsc millimeters 21.000 bsc 21.000 bsc 3.84 bsc 1.270 bsc
49 tspc603r 5410a?hirel?10/04 cerquad 240 package figure 19. mechanical dimensions of th e wire-bond cerquad package millimeters dim min typ max a 30.86 31.00 31.75 b 30.86 31.00 31.75 c 3.67 3.95 4.15 d 0.185 0.220 0.270 e 3.10 3.50 3.90 f 0.175 0.200 0.225 g 0.50 bsc he 2.025 2.100 2.175 j 0.130 0.147 0.175 k 0.45 0.50 0.55 p 0.25 bsc s 34.41 34.58 34.75 u 17.20 17.30 17.40 v 34.41 34.58 34.75 w 0.45 0.70 0.95 y 17.20 17.30 17.40 z 0.122 0.127 0.132 aa 1.80 ref ab 0.95 ref 21 4 7 wire bonds ceramic body alloy 42 leads die 0.16 tm l-n s a 4 x 60 tips u v b y 180 121 80 1 181 120 240 81 l n view ac 4 places m 0.20 m s h l-n s m view ae datum plane aa x = l, m or n view ac x p g ad ad section ad 240 places top ce w view ae t seating plane datum plane h 0.10 h he k 2 ab 0.08 m s t l-n s m d f z j notes: 1. dimensioning and tolerancing per asmey14.5m-1994 2. controlling dimension: millimeter 3. datum plane h is located at bottom of lead and is coincident with the lead where the lead exists the ceramic body at the bottom of the parting line 4. datum l. m and n to be determined at datum plane h 5. dimension s and v to be determined at seating plane t. 6. dimension a and b define maximum ceramic body dimensions including glass protrusion and top and bottom mismatch
50 tspc603r 5410a?hirel?10/04 ordering information ordering information of the cbga and ci-cga packages prefix temperature range : t c m: -55, +125?c v: -40, +110?c screening level: package : g: cbga gs: ci-cga ts pc603r m g 12 b /q l bus divider (to be confirmed) l: any bus at 75 mhz maximum internal processor speed 6 : 166 mhz 8 : 200 mhz 10: 233 mhz 12: 266 mhz 14: 300 mhz (x) type prototype (c) revision level __ : standard b/q: mil-prf-38535, class q u: upscreening
51 tspc603r 5410a?hirel?10/04 ordering information of the cerquad 240 package note: for availability of the different ve rsions, contact your atmel sales office. prefix temperature range: t c m: -55, +125?c v: -40, +110?c c: 0, +70?c screening level: package: a : cerquad ts pc603r m a 8 b /q l maximum internal processor speed 6: 166 mhz 8: 200 mhz (x) type prototype (c ) revision level b/q : mil-prf-38535, class q __ : standard bus divider (to be confirmed) l: any bus 66 mhz definitions datasheet status validity objective specification this datasheet contains target and goal specifications for discussion with the customer and application validation before design phase target specification this datasheet contains target or goal specifications for product development valid during the design phase preliminary specification site this datasheet contains prel iminary data. additional data may be published at a later date and could include simulation results valid before characterization phase preliminary specification site this datasheet also contains characterization results valid before the industrialization phase product specification this datasheet contains final product specifications valid for production purpose limiting values limiting values given are in accordance with the absolute maximu m rating system (iec 134). stresses above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sect ions of the specification is not implied. exposure to limitin g values for extended periods may affect device reliability. application information where application information is given, it is advis ory and does not form part of the specification
52 tspc603r 5410a?hirel?10/04 life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can r easonably be expected to result in personal injury. atmel customers using or selling these products for use in such applications do so at their own risk and agree to fully indem nify atmel for any damages resulting from such improper use or sale. document revision history table 18 provides a revision histor y for this hardware specification. table 18. document revision history revision number date substantive change(s) a 10/2004 this document is a merge of tspc603r in cbga255/ci-cga 255 package (ref 2125b) and tspc603r in cerquad package (ref 2127a)
1 5410a?hirel?10/04 table of contents features .............. .............. .............. ............... .............. .............. ...........1 features specific to cbga 255 and ci-cga 255 ................................................ 1 features specific to cerquad ............................................................................... 1 description ......... .............. .............. ............... .............. .............. ...........1 screening/quality/packaging .... ................ ................. .............. .......... 2 block diagram............ ................. ................ ................. .............. ...........2 overview ........... ................ .............. ............... .............. .............. ...........3 signal description ............... .............. .............. .............. .............. ........ 4 detailed specifications ...... .............. .............. .............. .............. .........5 applicable documents ......... ................ ................. ................ ..............5 design and construction ...................................................................................... 5 terminal connections ................................................................................... 5 lead material and finish ............................................................................... 5 absolute maximum ratings .................................................................................. 5 absolute maximum ratings for the 603r ..................................................... 5 recommended operating conditions ........................................................... 6 thermal characteristics ......... ................. ................ ................. ...........6 cbga 255 and ci-cga 255 packages ................................................................ 6 cerquad 240 package ...................................................................................... 7 thermal management example.................................................................... 8 power consideration ............ ................ ................. ................ ..............8 dynamic power management ............................................................................... 8 programmable power modes ............................................................................... 9 power management modes .................................................................................. 9 power management software considerations ................................................... 11 power dissipation ............................................................................................... 12 marking ............................................................................................................... 12 pin assignments ....... ................. ................ .............. .............. ............13 cbga 255 and ci-cga 255 packages .............................................................. 13 pinout listing .............................................................................................. 14 cerquad 240 package .................................................................................... 16 pinout listing .............................................................................................. 17 electrical characteristics ..... ................ ................. ................ ............21 general requirements ........................................................................................ 21 static characteristics .......................................................................................... 21
2 5410a?hirel?10/04 dynamic characteristics ..................................................................................... 22 clock ac specifications.............................................................................. 22 input ac specifications ............................................................................... 23 output ac specifications ............................................................................24 jtag ac timing specifications.......................................................................... 26 functional description ........... ................. ................ .............. ............27 powerpc registers and programming model .................................................... 27 general-purpose registers (gprs) ............................................................ 28 floating-point registers (fprs) .................................................................. 28 condition register (cr) .............................................................................. 28 floating-point status and control register (fpscr) ................................. 28 machine state register (msr) ................................................................... 28 segment registers (srs) ........................................................................... 28 special-purpose registers (sprs) ............................................................. 29 instruction set and addressing modes ...............................................................32 powerpc instruction set and addressing modes ....................................... 32 powerpc 603r microprocessor instruction set .......................................... 34 cache implementation ........................................................................................ 34 powerpc cache characteristics ................................................................. 34 powerpc 603r microprocessor cache implementation ............................. 34 exception model ......................................................................................... 35 powerpc exception model ......................................................................... 35 powerpc 603r microprocessor exception model ...................................... 37 memory management ......................................................................................... 39 powerpc memory management ................................................................. 39 powerpc 603r microprocessor memory management .............................. 40 instruction timing ........................................................................................ 40 preparation for delivery ..... ................ ................. ................ ..............42 packaging ........................................................................................................... 42 certificate of compliance .................................................................................... 42 handling .............................................................................................................. 42 choice of clock relationships ............................................................................43 system design information ... ................. ................ .............. ............45 pll power supply filtering ................................................................................ 45 decoupling recommendations........................................................................... 45 connection recommendations........................................................................... 45 pull-up resistor requirements ........................................................................... 46 package mechanical data .. ................ ................. ................ ..............46 cbga package parameters ............................................................................... 46 mechanical dimensions of the cbga package ........................................... 47 ci-cga package parameters ............................................................................. 47 mechanical dimensions of the ci-cga package ....................................... 48 cerquad 240 package .................................................................................... 49
3 5410a?hirel?10/04 ordering information ............ ................ ................. ................ ............50 ordering information of the cbga and ci-cga packages ................................ 50 ordering information of the cerquad 240 package ........................................ 51 definitions ............. ................ ................ ................. ................ ............51 life support applications .................................................................................... 52 document revision history ................. ................. ................ ............52
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